The present invention relates to improved means and methods for generating a longitudinal parity word for a predetermined plurality of words stored in a digital computer memory.
It is well known in the art to provide for checking and/or correcting of digital data by the provision of one or more "parity" bits along with a group of data bits. Typically, each word of a data group comprising a predetermined plurality of horizontally arranged words may be provided with a horizontal parity bit, and each column of the data group may be provided with a longitudinal parity bit. As is well known, by appropriately combining these parity and longitudinal parity bits, error detection may be achieved and also, in appropriate cases, error correction may additionally be provided. For example, if it is assumed that there is only a single bit error in the bits of a data group, then the horizontal parity bit will identify the particular word containing the error bit, while the longitudinal parity bit will identify the particular column of the word containing the error bit. Accordingly, such a single error bit in a data group is not only uniquely identified, but also may be appropriately corrected by correction circuitry well known to those in the art.
Although the provision of horizontal and longitudinal parity bits in a data group is generally desirable, the cost of the additionally required hardware and/or software must be balanced against the advantages to be gained. In particular, it has often been found to be uneconomical to provide for the continuous generation of longitudinal parity for a plurality of words stored in a digital memory. Attempts to solve this problem for a digital computer memory have been proposed, such as disclosed for example in U.S. Pat. No. 3,887,901, but even the reduced hardware proposed by this patent is not sufficiently economical for many applications.